One of the long-standing objectives in the advancement of semiconductor technology is scaling. Technology scaling results in higher integration of semiconductor components, such as transistors, interconnections, etc. However, technology scaling poses several challenges, such as requiring stricter design rules along with smaller process margins to overcome greater process variation, tool development, etc.
Fabrication of interconnect structures by dual damascene integration scheme has been widely adopted for advanced technology nodes. The dual damascene integration scheme involves forming conductive lines and its underlying interconnect vias in a same deposition step. For such interconnect via fabrication, conventional fabrication processes are often inadequate to produce smaller geometries with the required structural integrity. Undesirable tapered profiles can form at the top and/or sidewalls of the interconnect vias and may cause unwanted deviation from electrical design specifications, thereby compromising the quality and reliability of the semiconductor device. The conventional approach to reducing the dimensions of IC devices is to rely on improvements to the photolithographic process, however, such improvements can be time consuming and costly.
For the reasons described above, there is a strong need for chamferless interconnect via fabrication methods that can provide interconnect vias with improved structural integrality and reliability.